As circuit density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. One additional technique finding greater application in achieving increased circuit density is to form field effect transistors with thin films (i.e., polysilicon films of less than or equal to 1500 Angstroms thickness), which is commonly referred to as "thin film transistor" (TFT) technology. These transistors are formed using thin layers which constitute all or a part of the resultant source and drain regions.
Specifically, typical prior art TFT's are formed from a thin film of semiconductive material (typically polysilicon). A central channel region of the thin film is masked by a separate layer, while opposing adjacent source/drain regions are doped with an appropriate p or n type conductivity enhancing impurity. A gate insulator and gate are provided either above or below the thin film channel region, thus providing a field effect transistor having source/drain and channel regions formed |within a thin film as opposed to a bulk substrate.
Literature reports have shown that it is possible to enhance the performance of thin film transistors, and particularly polysilicon thin film transistors, by using a drain offset between the channel region and the drain region. The prior art literature reports provision of such layer so to have a doping concentration identical to that of the channel region, or more preferably to have a lower dopant concentration of the opposite conductivity type.
Utilization of drain offset regions in thin film transistors is particularly advantageous in static random access memory (SRAM) cell and active matrix display constructions. Typical resistor load SRAM cells are not suitable for high density SRAMs as the resistor loads do not provide desired low leakage, cell stability or alpha-particle immunity. The polysilicon TFT loads in six transistor stacked CMOS SRAM cells can provide the required low leakage while providing high ON currents at the same time which makes the cell more immune to alpha particle hits or high junction leakage. Such transistors are more suitable for high density SRAMs. The drain offset region in such transistors reduces the electric field near the drain which reduces the leakage, but this also has an adverse effect on the ON current.
Attributes of the invention will be more readily appreciated by an initial description of two prior art processes for producing thin film transistors having drain offsets. For example, FIG. 1 illustrates a semiconductor wafer fragment 10 comprised of a substrate 12. An insulating layer 13 is provided thereover, and includes an intervening or embedded electrically conductive transistor gate 14. That portion of substrate 12 immediately beneath layer 13 and gate 14 would comprise an insulator material. A gate dielectric layer 16 overlies insulating layer 13 and gate 14. Further, a thin film transistor layer 18 is provided over gate dielectric layer 16.
In accordance with prior art methods, thin film transistor layer 18 is subjected to a blanket implant, in this described example an n-type dopant, to some suitable first low concentration, such as 5.times.10.sup.17 atoms/cm.sup.3 -1.times.10.sup.18 atoms/cm.sup.3. The function of the blanket implant is to provide desired resultant semiconductivity (i.e., conductivity that can 16 be selectively "on" or "off" dependent upon selected gate voltage) for the channel region of the transistor.
Referring to FIG. 2, a mask 19 is provided over thin film transistor layer 18 to define a desired n-type channel region 20 overlying gate 14. Wafer 10 is then subjected to p-type doping to provide an example p- implant concentration outside of mask 19 to provide an example p- concentration of from 5.times.10.sup.17 atoms/cm.sup.3 -5.times.10.sup.18 atoms/cm.sup.3. The purpose of such implant is to counterdope the blanket n-type implant previously provided to produce a desired drain offset region doping.
Referring to FIG. 3, channel region 20 and what becomes a desired drain offset region 24 are masked with a photoresist masking block 25. Wafer fragment 10 is then subjected to heavy p-type doping to provide a resultant p+ concentration of, for example, greater than or equal to 1.times.10.sup.19 atoms/cm.sup.3. The result is provision of desired source and drain regions 26 and 27, respectively. The effect is to produce a lighter doped drain offset region of the same conductivity type as the source and drain regions between the channel and drain regions.
An alternate prior art method of producing thin film transistors having drain offsets is described with reference to FIG. 4. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix "a", or with different numerals. FIG. 4 in this described embodiment depicts a processing step immediately subsequent to the FIG. 1 processing step of the first described embodiment. Here, a masking block 19a is patterned to overlap or extend laterally beyond the confines of gate 14 to provide a source offset region 17 and a drain offset region 24a. The wafer is then subjected to heavy p+ doping to produce the illustrated source and drain regions 26a and 27a, respectively. Therefore in accordance with this described prior art embodiment, the resultant drain offset region 24a is provided to be of the same identical concentration and conductivity type as that of channel region 22.
Yet another alternate prior art embodiment and method is shown in FIGS. 5 and 6. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix "b" or with different numerals. FIG. 5 illustrates a wafer fragment 10b shown at a processing step immediately subsequent to that depicted by FIG. 1 of the first described embodiment. Here, a photoresist masking layer 19b is patterned to provide an opening 21 effective for producing a desired drain offset region 24. The wafer fragment is then subjected to light p-type doping, yet to a concentration sufficient to overwhelm the n- concentration previously provided in drain offset region 24 by the FIG. 1 blanket implant.
Referring to FIG. 6, masking block 25 is provided and the wafer subjected to p+ doping to effectively produce the same resultant prior art construction of FIG. 3.
The prior art also has recognized improvements in operation by gating the drain offset region, such as reported in our prior art paper, Batra et al. "Development of Drain-Offset (DO) TFT Technology For High Density SRAMs, Extended Abstracts" Oct. 1994, pp. 677-678.
This invention concerns improvements in method of producing thin film transistors having gated drain offsets.